This invention broadly relates to a semiconductor memory device, and a method for replacing a redundant circuit. More specifically, this invention is directed to a semiconductor memory device which has an improved redundant subword selection circuit in a subword system.
With recent reduction of a semiconductor device in size, an LSI (Large scale integrated circuit) having the semiconductor device has become popular.
For example, a dynamic type random access memory (DRAM) or a synchronous random access memory (SDRAM) has been used as a semiconductor memory device having capacity of 256 Mbit for one chip.
In such a semiconductor memory device, a memory cell array is divided into a plurality of banks. With this structure, a redundant memory cell array, namely, a redundant memory region is provided outside a main memory in each bank.
Herein, a normal memory cell array is arranged in the main memory while a spare memory cell array is placed in the redundant memory cell array.
Meanwhile, suggestions have been made in the art about a word shunt system with respect to word line selection for selecting a predetermined memory cell.
In such a word shunt system, a gate wiring pattern (wiring line) and a metal pattern (metal line) having low resistance are alternately wired in parallel as a wiring method for improving writing/reading speed.
However, it is becoming difficult to form a metal wiring layer for the word shunt in accordance with the pitch of the memory cell with large capacity memory.
To solve this problem, use generally has been made of a subword system in which a subword driver is arranged in the memory cell array so as to designate via the subword driver.
In the above-discussed semiconductor memory device of the sub-word system, application has been made about a defect relieving technique in which a spare redundant memory cell array is used instead of the defective memory when a defect is detected in a part of the main memory.
In other words, even when a small number of defects occur in the main memory region in a production process, the total function of the semiconductor memory device will not be damaged.
In such a semiconductor memory device having a redundant circuit, an electrical characteristic test is carried out in a wafer-selecting step during the production process.
As the result of the test, when the defect exists in the memory cell array, the address of the memory cell array having the defect is programmed with a fuse arranged inside the redundant circuit.
Thereby, the writing/reading operation is halted for a defective memory cell in the main memory region, and the writing/reading operation is performed by the redundant memory cell in the redundant memory region.
In this event, the switching to the redundant memory cell is carried out at every word line and every bit line. Under this circumstance, address information of the defective portion is necessary in the switching for each word line while bit position information of the defective portion is required for each bit line.
Namely, when the defective memory cell is detected, the position of the fuse to be cut is determined on the basis of the address information of the defective portion, and the fuse is, for example, fused by irradiating it with a laser beam. With this fusing, the position of the defective memory cell is written to a ROM fuse.
As described above, the position of the defective memory cell is written to the fused ROM. Consequently, when the memory corresponding to the cut fuse is selected, the switching is carried out such that the redundant memory region is selected in lieu of the main memory.
More specifically, the address of the memory cell in the selected main memory region is compared with the address of the defective memory cell in the redundant memory region. In the comparison result, if the defective memory cell is selected, the redundant memory cell in the redundant memory region will be accessed.
As discussed before, the number of necessary redundant memory cells is also increased with the increase of the memory capacity of the semiconductor memory device.
Accordingly, it is important to reduce the number of component elements of the semiconductor memory device as small as possible in order to efficiently arrange the increased number of redundant memory cells.
Referring to FIG. 1, a related memory cell array will now be described.
Such a memory cell array is divided into two banks, an A bank and a B bank in an X-direction (a lateral direction), and is divided into two banks in a Y-direction (a vertical direction). Thereby, the memory cell array is divided into four areas consisting of an upper bank A, a lower bank A, an upper bank B, and a lower bank B.
With such a structure, one bank, for example, the A bank, has a memory capacity of 32 M bits, and is further divided into 16 plates of A0Pxcx9cA15P. Each of the plates A0P and A1P is composed of one plate. The one plate (a portion indicated by oblique lines in the figure) has 2M bits, and 512 word linesxc3x974K bit lines. In the 512 word lines, the address is composed of 9 bits of X0xcx9cX8.
A word driver block 11 is arranged in the X-direction, and a driving word line is lined up although not shown. Further, a bit line is arranged so as to cross with a main word line extended in the Y-direction from the word driver block, although also not shown.
The selection of the memory cell is carried out by selecting the word line arranged in the X-direction by the use of the X-address and by selecting the bit line arranged in the Y direction by the use of the Y address.
Under this circumstance, a data signal is written/read for the selected memory cell by selecting the memory cell positioned at the portion where the word line and the bit line are crossing.
In the above-mentioned semiconductor memory device, the word driver for driving the word line of the memory cell array is connected to a backed metal wiring pattern (line) such as an aluminum pattern in the output thereof, and is constituted with the same pitch as the polysilicon wiring pattern and the aluminum wiring pattern.
However, the reduction in size has advanced with the large capacity of the LSI, as described above. In consequence, it is becoming difficult to pattern the aluminum line with the pitch of the polysilicon wiring line connected to the gate of the memory cell.
Further, the height of the formation layer in a memory cell portion on a semiconductor substrate becomes higher. Under this circumstance, it is difficult to pattern the aluminum line because of projections or protrusions occurred in a boundary thereof.
To solve such a problem, a division word driver system, which can readily avoid passing through the aluminum line in the memory cell portion, has been adopted recently.
In this system, a word driver is divided into a main word driver and a subword driver. With such a structure, the subword driver is selected by the main word line for driving with main word driver, and the selected subword driver drives the word line (subword line) for selecting the memory cell.
Referring now to FIG. 2, for example, when one main word line MWE is selected, subword drivers SWD21a, 21b, and 21c, which are connected to the main word line MWE, are selected and activated.
The sub-word drivers SWD 21a, 21b and 21c are arranged at both sides of a memory cell line in parallel with a bit line pair. Herein, subword lines SW00xcx9cSW13, which are produced from the subword lines at the both sides, are arranged so as to form a comb structure with each other by sandwiching the memory cell.
For example, the subword driver SWD 21b is connected to subword lines SW11 and SW13 at right and left sides thereof. Herein, the subword lines SW11 and SW13 designate the memory cell at even number lines of memory cell lines arranged at right and left sides.
The subword driver SWD21a is connected to subword lines SW00 and SW02, which designates the memory cell corresponding to a normal rotation bit line T among bit line pairs at right and left sides.
The subword driver 21c is connected to the subword lines SSW20 and SW22, which designate the memory cell corresponding to the normal rotation bit line T at right and left sides.
With this structure, one subword line is selected and driven by the use of subword selection signals SWE0xcx9cSWE3 given to the subword driver, so that the cell 11 is selected.
For example, when the subword selection signals SWE0xcx9cSWE3 are equal to xe2x80x9cHxe2x80x9d, xe2x80x9cLxe2x80x9d, xe2x80x9cLxe2x80x9d, xe2x80x9cLxe2x80x9d, respectively, the subword lines SW00 and SW20 are driven, and thereby, the cell 11 connected to the subword lines SW00 and SW20 is selected. For example, when SW0 is selected, the subword lines SW00 and SW20 are selected.
Further, the X-redundant circuit for replacing the word line and the Y-redundant circuit for replacing the bit line have been arranged such that optimum arrangement can be carried out in the related semiconductor memory device.
However, a buffer is arranged in a read/write bus portion, and a data signal is transferred between the memory cell and the buffer at high speed.
A virtual channel SDRAM of 64M/128M having such specification has been put into use. It is predicted that such product will have a large commercial appeal. In this specification, the Y-redundant circuit cannot be sufficiently provided because priority is given to the speed so as to decrease the chip area.
To this end, the main word replacing method is supplanted by the subword replacing method for replacing with a subword unit, and the replacing unit is subdivided so as to improve replacing efficiency. Thereby, the lack of the Y-redundant circuit can be compensated for.
Herein, the unit of the subword drivers selected by the main word line is collectively replaced in the main word replacing method.
Referring to FIG. 3, the related block layout comprises a one plate memory array 11, a redundant circuit 21, a sense amplifier (hereinafter, may be referred to as S.A in the figure) 31, a main word driver 51, and a redundant main word driver 81.
A subword selection circuit 1110 and a redundant subword selection circuit 1120 are adjacently arranged in the Y-direction of the memory array 11.
The subword line is selected with the address by the subword driver (not shown) which is positioned in the region where the main word line 61 of the selected memory cell array 11 and the subword selection signal 41 are crossing. Thereby, the memory cell is selected.
In the reading operation, the data signal read out from the memory cell is transferred to the bit line 102, and is amplified in the sense amplifier 31 for the data line 110.
The subword selection signal 41 is commonly wired on the plate n and the plate n+1. The redundant subword selection signal 91 is commonly wired to the redundant circuits of the plate n and the plate n+1.
Referring to FIG. 4, the arrangement of the buffer 1140 and the data transfer line 113 are different from FIG. 3.
Further, the subword selection circuits 1110 of the plate n and n+1 are arranged adjacent to the main word driver under the plate. The redundant subword selection circuit 1120 is also arranged adjacent to the main word driver under the redundant circuit. Moreover, the redundant subword selection signal 91 and the subword selection signal 41 are wired in the perpendicular direction.
Typically, the number of buffers 1140 and the data transferring lines 113 is higher to enhance transfer efficiency. For example, the number of the data transfer lines is equal to 1 k for 4 k of bit lines. In this condition, the data signals of 1 k bit are collectively transferred from the memory cell of 4 K bit to the buffer.
To this end, considering the layout efficiency, the buffer 1140 is adjacently arranged in the Y-direction of the plate n+1. The subword selection circuit 1110 and the redundant subword selection circuit 1120 are placed adjacent to the main word driver.
In this event, the layout is carried out by corresponding to the X direction width of the redundant circuit 21 with the width of the redundant subword selection circuit 1120. Consequently, the layout inevitably becomes complex.
Referring to FIG. 5, a plate nxe2x88x92100 includes a subword selection circuit block 124, subword selection signal lines (four line bundle) 114xcx9c117, subword drivers 121axcx9c121e, a memory cell array, a redundant subword selection block 127, redundant subword drivers 122axcx9c122e, redundant subword selection signals 121xcx9c134, and a redundant memory cell array.
Similarly, a plate n+1xe2x88x92200 includes a subword selection circuit block 224, subword selection signal lines (bundle of four lines) 214xcx9c217, subword drivers 221axcx9c221e, a memory cell array, a redundant subword selection block 227, redundant subword drivers 222axcx9c222e, redundant subword selection signals 231xcx9c234, and a redundant memory cell array.
With such a structure, the main memory is selected by the use of the subword selection circuit blocks 124 and 224 while the memory of the redundant circuit is selected by the use of the redundant selection circuit blocks 127 and 227.
Referring to FIG. 6, the subword selection circuit block 124 comprises a block of subword selection circuits 301 to 304 which produces subword selection signals SWE00xcx9cSWE03 (line bundle 114), a block of subword selection circuits 311 to 314 which produces subword selection signals SWE10xcx9cSWE13 (bundle 115 of lines), a block of subword selection circuits 321 to 324 which produces subword selection signals SWE20xcx9cSWE23 (line bundle 116), and a block of subword selection circuits 331 to 334 which produces subword selection signals SWE30xcx9cSWE33 (line bundle 116).
The subword selection circuit illustrated in FIG. 7 contains a first CMOS inverter which is given a subword decode signal X0, a first N channel MOS transistor N2 which is given a first plate selection signal PSn between a source of an N-channel MOS transistor N1 of the inverter and a ground potential, a second N-channel MOS transistor N3 which is given a redundant non-selection signal REB, and a third N-channel MOS transistor N4 which is given a subword decode signal X1X2, and all these elements are connected in series.
With this structure, an output of the first MOS inverter is pull-up to a power supply potential VBOOT via a first P-channel MOS transistor P2, and a second MOS inverter receives the output of the P-channel MOS transistor to produce the output as a first subword line selection signal SWEn. The output of the second MOS inverter is also provided to the gate of the P channel transistor P2.
In the subword selection circuit, a redundant non-selection signal REB is put into an xe2x80x9cLxe2x80x9d level when replacing, and is inactivated. When the redundant non-selection signal REB is put into an xe2x80x9cHxe2x80x9d level when not replacing, a plate selection signal Ps is put into an xe2x80x9cHxe2x80x9d level, the subword decode signal X0 is put into an xe2x80x9cHxe2x80x9d level in a lower address signal, and a lower address signal X1X2 is put into an xe2x80x9cHxe2x80x9d level. Consequently, the selected subword selection signal SWE is put into an xe2x80x9cHxe2x80x9d level. When replacing, the redundant non-selection signal REB is put into an xe2x80x9cLxe2x80x9d level, resulting in inactivation.
Referring to FIG. 8, the redundant subword selection circuit block includes a block of redundant subword selection circuits 361 to 364 which produces redundant subword selection signals RSWE00xcx9cRSWE03 (bundle 131 of lines), a block of redundant subword selection circuits 371 to 374 which produces redundant subword selection signals RSWE20xcx9cRSWE23 (bundle 133 of lines), a block of redundant subword selection circuits 381 to 384 which produces redundant subword selection signals RSWE20xcx9cRSWE23 (bundle 116 of lines), and a block of redundant subword selection circuits 391 to 394 which produces redundant subword selection signals RSWE30xcx9cRSWE33 (bundle 134 of lines).
The redundant subword selection circuit illustrated in FIG. 9 is different from the above-mentioned subword selection circuit in that an inverter IV is connected to the gate of the N-channel MOS transistor N3 which is provided with a redundant non-selection signal REB.
Specifically, the subword selection circuit and the redundant subword selection circuit have a complementary relationship for the redundant non-selection signal REB.
For example, when replacing, the redundant non-selection signal REB is put into an xe2x80x9cLxe2x80x9d level; the plate selection signal PSn is put into an xe2x80x9cHxe2x80x9d level, the subword decode signal X0 is put into an xe2x80x9cHxe2x80x9d level; and the redundant selection signal RS is put into an xe2x80x9cHxe2x80x9d level. Thereby, an xe2x80x9cHxe2x80x9d level appears for the selected redundant subword selection signal RSWEn.
In the meantime, when not replacing, the redundant non-selection signal REB becomes an xe2x80x9cHxe2x80x9d level, resulting in inactivation.
Namely, when the redundant non-selection signal REB is equal to an xe2x80x9cHxe2x80x9d level, the replacement is not carried out. Consequently, the memory cell array of the main memory is selected, and the redundant memory region is not selected.
Conversely, when the redundant non-selection signal REB is equal to an xe2x80x9cLxe2x80x9d level, the memory cell array of the main memory region is not selected, and the redundant memory region is selected.
The main word driver circuit illustrated in FIG. 10 and the redundant main word driver circuit illustrated in FIG. 11 are similar to the above-mentioned subword selection circuit in the basis structure.
Specifically, VBOOT is supplied to the power supply potential in the main word driver circuit. Further, decode signals of addresses X3 to X5 are given as input signals. A plate selection signal PSn and decode signals of addresses X6 to X8 are given as the other condition input signals. Further, MWEnm is produced as the main word selection signal.
The redundant main word driver circuit inputs only the plate selection signal PSn as the input condition signal, and does not input the decode signals of the addresses X6 to X8 to produce the redundant main word line RWE different from the main word driver circuit.
Referring to FIG. 12, a subword driver circuit includes transistors N13, N15, N17, and N19 which are commonly given with VBOOT and are commonly connected to the main word line via the drain thereof, and transistors N14, N16, N18, and N20 which are connected to the corresponding gate via the sources of the transistors N13xcx9cN19, and are connected to output lines corresponding to the respective subword selection circuits via the drains.
With such a structure, the sources of the transistors N14, N16, N18, and N20 are connected to subword selection signal lines SWnm, SWnm+2, SWnm+4, and SWnm+6, respectively, and are branched so as to be connected to the memory cell array arranged in the upward and downward directions of the Y-direction.
As discussed above, the subword selection signal lines are arranged in a comb form. In consequence, the sources of the subword driver transistors N14, N16, N18, and N20, which are arranged at the opposite side via the memory cell array, are connected to the subword selection signal lines SWnm+1, SWnm+3, SWnm+5, and SWnm+7, respectively.
For example, in the memory cell sandwiched between the subword drivers 122b and 122c, the word line corresponding to the normal rotation bit line T among the bit line pairs representing by SW00, SW02, SW04, and SW06 is activated by the use of the subword driver 122b while the word line corresponding to the normal rotation bit line B among the bit line pairs representing by SW01, SW03, SW05, and SW07 is activated by the use of the subword driver 122c. 
In a subword decoder block 403 illustrated in FIG. 13A, an address X0 becomes an inversion signal XON by an inverter IV1, and becomes a normal rotation signal X0T by inverters IV2, IV3.
Namely, when the address X0 is equal to an xe2x80x9cLxe2x80x9d level, the inversion signal XON becomes an xe2x80x9cHxe2x80x9d level, and the normal rotation signal X0T becomes an xe2x80x9cLxe2x80x9d level.
In the meantime, when the address X0 is equal to an xe2x80x9cHxe2x80x9d level, the inversion signal XON becomes an xe2x80x9cLxe2x80x9d level, and the normal rotation signal X0T becomes an xe2x80x9cHxe2x80x9d level.
Referring to FIG. 13B, X1N2N=xe2x80x9cLxe2x80x9d, xe2x80x9cLxe2x80x9d=0, X1T2N=xe2x80x9cHxe2x80x9d, xe2x80x9cLxe2x80x9d=2, X1N2T=xe2x80x9cLxe2x80x9d, xe2x80x9cHxe2x80x9d=1, X1T2T=xe2x80x9cHxe2x80x9d, and xe2x80x9cHxe2x80x9d=3 are produced as the X12 decode signal, depending upon the state of the addresses X1 and X2.
Subsequently, description will be made about an operation on the basis of the above-mentioned structure with reference to FIG 14.
At time prior to time t1, a pre-charge state is kept, and all of the subword decode signals are put into xe2x80x9cLxe2x80x9d levels. In this case, the address is set so as to select the plate n.
At time t1, a command and an address are synchronized with rising of a clock. Herein, a command referred to as xe2x80x9cactivexe2x80x9d serves to select a word.
At time t2, the selection signal PSn of the plate n becomes an xe2x80x9cHxe2x80x9d level while decode signals X345 and X678 of addresses X3, X4, X5 and X6, X7, X8 become xe2x80x9cHxe2x80x9d levels. Further, X0 and X1X2 serving as the subword decode signals also become xe2x80x9cHxe2x80x9d levels.
When a redundant main word active signal PXR becomes an xe2x80x9cHxe2x80x9d level, a precharge signal PRC also becomes an xe2x80x9cHxe2x80x9d level, a redundant address is detected and replaced, at time T3, a redundant selection signal RSpq is put into an xe2x80x9cHxe2x80x9d level, and a redundant non-selection signal REBp is put into an xe2x80x9cLxe2x80x9d level.
At time t4, the selected main word signal MWEnm becomes an xe2x80x9cHxe2x80x9d level and a redundant main word signal RWEn becomes an xe2x80x9cHxe2x80x9d level by decode signals X345 and X678 of X3, X4, X5 and X6, X7, X8.
At time t5, the redundant subword selection signal RSWEn of the plate n is generated. At time t6, the redundant subword signal RSWn of the plate n is selected.
When not replacing, in the timing chart illustrated in FIG. 14, at time t3, a redundant selection signal RSpq becomes an xe2x80x9cLxe2x80x9d level, and a redundant non-selection signal REBp becomes an xe2x80x9cHxe2x80x9d level.
At time t4, the main word line MWEnm selected by decode signals X345 and X678 of X3, X4, X5 and X6, X7, X8 is put into an xe2x80x9cHxe2x80x9d level, and the redundant main word line RWE is put into an xe2x80x9cLxe2x80x9d level.
At time t5, the subword selection signal SWEn of the plate n is generated. At time t6, the subword line SWn is selected.
In the above-mentioned related semiconductor memory device using the subword system, the subword selection circuit and the redundant subword selection circuit are provided at every plate. Consequently, the layout area of these circuits occupied on the chip inevitably becomes large.
In the related technique, the subword selection circuit is arranged on an extending line in Y-direction of the memory cell array. The subword selection signal line as the output thereof is extended and arranged in the Y-direction in the memory cell region.
In this condition, a predetermined number of subword lines are branched and arranged so as to extend from the subword selection line serving as a main line in the Y-direction parallel to the X axis. Thereby, a layout is formed so as to cross with the main word selection line in the Y-direction so as to reduce the affect of the layout.
However, in the case where the buffer is arranged in parallel adjacent to the Y-direction of the memory array, the subword selection circuit is arranged adjacent to the main word driver. As a consequence, the wiring structure becomes complex.
In addition, in the case of the subword replacing method, the redundant subword selection circuit has a substantially equivalent scale with the subword selection circuit.
However, the redundant subword selection circuit is arranged so as to match with the width of the redundant circuit. Consequently, the layout further becomes complex, so that the layout area becomes large.
It is therefore an object of this invention to provide an improved subword selection circuit in a subword system.
It is another object of this invention to provide a semiconductor memory device and a redundant circuit replacing method in which the redundant subword selection circuit is eliminated at every plate.
In a semiconductor memory device according to one aspect of this invention, a plurality of banks are arranged on a semiconductor substrate. A plurality of plates are also arranged, and a plurality of memory array groups are arranged on the plates.
Redundant memory cell array groups replace a memory cell array including a defective memory cell and are arranged at every plate. Subword selection circuits switch subword selection lines at every plate.
With such a structure, each of the subword selection circuits has a selection unit which selects a subword selection line on the plate belonging thereto and a redundant subword selection line of the redundant memory cell array arranged on the other adjacent plate.
The subword selection line is selected by the use of a subword driver, and predetermined redundant subword lines of the memory cell array and the redundant memory cell array are selected after an arbitrary main word line is selected by a row decoder during selecting a word line.
In a semiconductor memory device according to another aspect of this invention, a plurality of plates are arranged on a semiconductor substrate at every bank.
Each of the plates includes memory cell array groups, subword driver groups which select word lines of the memory cell array groups, subword driver selection units which select one among the subword driver groups, redundant memory cell array groups which rep!ace a memory cell array group including a defective memory cell, redundant subword driver groups which select word lines of the redundant memory cell array groups, and a redundant subword selection unit which selects one among the redundant subword driver groups.
With this structure, the redundant subword selection unit commonly uses the subword selection units between the adjacent plates, and is given a subword selection signal generated by the subword selection unit of one plate as a redundant subword selection signal of the other plate in order to control selection of the word lines.
In a semiconductor memory device according to still another aspect of this invention, first and second plates are arranged on a semiconductor substrate at every bank.
Each of the plates includes memory cell array groups, subword driver groups which select word lines of the memory cell array groups, subword driver selection units which select one among the subword driver groups, redundant memory cell array groups which replace a memory cell array group including a defective memory cell, redundant subword driver groups which select word lines of the redundant memory cell array groups, and a redundant subword selection unit which selects one among the redundant subword driver groups.
With such a structure, both the subword selection unit and the redundant subword selection unit are commonly used by only the subword selection unit. The subword selection unit commonly used between the plates is commonly used between the first and second plates. The common use between the first and second plates is carried out by the subword selection unit which commonly uses the redundant subword selection lines of the first and second plates in the other plate to each other.
As described above, the semiconductor memory device has the subword selection circuits for switching the selection of the subword selection lines at every plate.
With this structure, each of the subword selection circuits has the selection unit for selecting the subword selection lines on the plate belonging thereto and the redundant subword selection lines of the redundant memory cell array arranged on the other adjacent plate.
Thereby, the subword selection circuit of the adjacent plate n, n+1 can be commonly used between these plates.
Consequently, 16 of the redundant subword selection signals specific to the conventional redundant wired inside the memory cell array for one plate, and 16 of the redundant subword selection circuits specific to the conventional subword selection circuit can be eliminated entirely according to this invention.
Further, the chip size can be reduced as the secondary effect. In consequence, both the package size and the mounting size can be reduced, and the consumption current can be lowered also.